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UM008101-0601 Serial Input/Output
296
Clear To Send, (D5). This bit is similar to the DCD bit, except that it shows
the inverted state of the CTS pin.
Transmit Underrun/End of Message (D6)
This bit is in a set condition following a reset, either internal or external.
The only the Reset Transmit Underrun/EOM Latch command (WR0, D6
and D7) can reset this bit. When the Transmit Underrun condition occurs,
this bit is set; causing the External/Status interrupt, which is reset by issuing
the Reset External/Status Interrupt command bits (WR0). This status bit,
along with other control bits, has an important function in controlling a
transmit operation. For more information, see “Bisync Transmit Underrun”
and “SDLC Transmit Underrun”.
Break/Abort (D7)
In the Asynchronous Receive mode, this bit is set when a Break sequence
(null character plus framing error) is detected in the data stream. The
External/Status interrupt, if enabled, is set when Break is detected. The
interrupt service routine must issue the Reset External/Status Interrupt
command (WR0, CMD2) to the break detection logic, enabling the Break
sequence termination to be recognized.
The Break/Abort bit is reset when the termination of the Break sequence is
detected in the incoming data stream. The termination of the Break
sequence also causes the External/Status interrupt to set. The Reset
External/Status Interrupt command must be issued to enable the break
detection logic to look for the next Break sequence. When a single extra-
neous null character is present in the receiver after the termination of a
break; it should be read and discarded.
In the SDLC Receive mode, this status bit is set by the detection of an
Abort sequence (seven or more 1s). The External/Status interrupt is handled
the same way as a Break. The Break/Abort bit is not used in the Synchro-
nous Receive mode.
- Z80 Family 1
- CPU Peripherals 1
- Table of Contents 3
- Direct Memory Access 4
- List of Figures 9
- UM008101-0601 List of Figures 10
- List of Figures UM008101-0601 11
- Parallel Input/Output 12
- Serial Input/Output 13
- List of Tables 15
- List of Tables UM008101-0601 17
- Z80 CPU Peripherals 18
- User Manual 18
- Counter/Timer Channels 19
- CTC ARCHITECTURE 20
- Structure of Channel Logic 21
- The Prescaler 23
- Interrupt Control Logic 25
- CTC PIN DESCRIPTION 27
- CTC OPERATING MODES 34
- CTC COUNTER Mode 34
- CTC TIMER Mode 35
- CTC PROGRAMMING 36
- Table6.TimeConstantRegister 40
- 76543210 40
- CTC Read Cycle 43
- CTC Counting and Timing 44
- CTC INTERRUPT SERVICING 45
- Return from Interrupt Cycle 47
- DMA Data Transfers 53
- DMA Characteristics 55
- Transfer Methods 56
- Modes of Operation 58
- Bus Control 59
- Programmability 59
- Figure 17. Modes of Operation 60
- Programming 63
- Classes of Operation 64
- <%2 72GTKRJGTCNU 65
- 7UGT/CPWCN 65
- <%272GTKRJGTCNU 66
- Figure 20) 70
- Transfer Speed 74
- Address Generation 75
- Variable Cycle 78
- Events and Actions 79
- I/O port address 85
- ,17(51$/6758&785( 89
- *HQHUDO2UJDQL]DWLRQ 89
- Address and Byte Counting 93
- Operations) 94
- Search Operations) 94
- Bus Requesting 96
- Bus Request Daisy-Chains 97
- Interrupt Vectors 100
- Interrupt Latches 102
- Interrupt On Ready 104
- Interrupt Service Routines 104
- Return From Interrupt 105
- Interrupt Daisy-Chains 106
- Polling for Service Requests 107
- PROGRAMMING 108
- Overview 108
- Table 13. DMA Status 109
- DISABLED ENABLED 109
- Write Registers 110
- Write Register 0 Group 111
- Source and Destination 112
- Port A Starting Address 112
- Block Length 113
- Write Register 1 Group 114
- Write Register 2 Group 116
- Write Register 3 Group 116
- Stop on Match 117
- Match Byte 117
- Mask Byte 117
- Interrupt Enable 117
- Write Register 4 Group 118
- Starting Address (Port B) 119
- Interrupts 119
- Interrupt Vector 120
- Pulse Generation 120
- Write Register 5 Group 121
- End-of-Block Action 122
- CE/WAIT Line Use 122
- Ready-Line State 122
- Reset (C3) 123
- ResetPortATiming(C7) 124
- ResetPortBTiming(CB) 124
- Load (CF) 124
- Continue (D3) 125
- Disable Interrupts (AF) 125
- Enable Interrupts (AB) 127
- Enable After RETI (B7) 128
- Read Status Byte (BF) 129
- Reinitialize Status Byte (8B) 129
- Read Mask Follows (BB) 130
- Initiate Read Sequence (A7) 131
- Force ReadY (B3) 131
- Read Registers 132
- Read Status Byte 133
- Initiate Read Sequence 133
- Reinitialize Status Byte 133
- Read Mask Follows 133
- Status Byte (RR0) 133
- Byte Counter (RR1, RR2) 135
- DMA Initialization 136
- Port Designation 138
- Address Loading 139
- Byte Matching (Searches) 142
- End-of-Block 143
- Auto Restart 143
- Force Ready Condition 143
- Variable Timing 144
- Enabling the DMA 144
- Reading Status 144
- Z80 DMA and CPU 147
- Chip Selection and Enabling 148
- Use of WAIT Input 150
- Simultaneous Transfers 151
- Bus Buffering 154
- Z80 DMA and Z80 SIO Example 157
- Table 18 158
- Bus Characteristics 163
- PERFORMANCE LIMITATIONS 167
- Bus Contention 167
- Control Overhead 168
- The CPU As Bus Master 169
- Reading Status Bytes 170
- The DMA As Bus Master 171
- (Searching is Optional) 174
- Search-Only 177
- Bus Requests 177
- Bus Release Byte-at-a-Time 178
- Bus Release on End-of-Block 179
- Bus Release on Match 180
- Bus Release on Not Ready 180
- REGISTER BIT FUNCTIONS 189
- Write Register Bit Functions 189
- Read Register Bit Functions 193
- Figure 1. PIO Block Diagram 197
- (8 Bits) 198
- Data Input 198
- PIN DESCRIPTION 200
- Figure 3. PIO Pin Functions 204
- PROGRAMMING THE PIO 207
- Loading The Interrupt Vector 208
- SelectingAnOperatingMode 209
- D6 D5 D4 D3 D0D2 D1 210
- Output Mode (Mode 0) 212
- Input Mode (Mode 1) 213
- Bidirectional Mode (Mode 2) 214
- Control Mode (Mode 3) 215
- INTERRUPT SERVICING 217
- APPLICATIONS 219
- I/O Device Interface 220
- V3 V2 V1 V0 221
- Control Interface 222
- PROGRAMMING SUMMARY 225
- Load Interrupt Vector 225
- Set Mode 225
- Set Interrupt Control 226
- Pin Functions 230
- Bonding Options 233
- CMOS Z80 240
- ARCHITECTURE 242
- Data Path 243
- Functional Description 246
- I/O Capabilities 247
- ASYNCHRONOUS OPERATION 250
- Asynchronous Transmit 252
- Asynchronous Receive 255
- SYNCHRONOUS OPERATION 258
- Monosync 260
- External Sync 260
- Synchronous Transmit 264
- Synchronous Receive 269
- SDLC (HDLC) OPERATION 275
- SDLC Transmit 276
- SDLC Receive 285
- 0001 1101 0000 1111 287
- Write Register 0 293
- Figure 114. Write Register 0 294
- Write Register 1 297
- Write Register 2 301
- Write Register 3 302
- Write Register 4 304
- Write Register 5 307
- Write Register 6 310
- Write Register 7 311
- Figure 122. Read Register 0 314
- Read Register 1 317
- Figure 123. Read Register 1 319
- Table 35. Interrupt Vector 320
- D7 D6 D5 D4 D3 D2 D1 D0 320
- V7 V6 V5 V4 V3* V2* V1* V0 320
- Figure 127. Data Concentrator 324
- Read Cycle 325
- Write Cycle 325
- Interrupt Acknowledge Cycle 326
- Return From Interrupt Cycle 327
- Daisy Chain Interrupt Nesting 328
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