Zilog Z08470 Manual do Utilizador descarregar pdf (Página 11)

Z80 CPU Peripherals

User Manual

List of Figures UM008101-0601

Direct Memory Access (continued)

Figure50. CE/WAITMultiplexer ...........................133

Figure51. SimultaneousTransferMultiplexer .................133

Figure52. SimultaneousTransfer ...........................134

Figure53. DelayingtheLeadingEdgeofMWR ................135

Figure54. DataBusBufferControlExample ..................138

Figure55. DMA-SIOEnvironment ..........................142

Figure 56. Connecting DMA to Demultiplexed Address/Data Buses 145

Figure 57. Z8000/Z80 Peripheral Interface ....................147

Figure58. DMABus-MasterGate(ByteorBurstModesOnly) ....149

Figure59. CPU-to-DMAWriteCycleRequirements ............151

Figure60. CPU-to-DMAReadCycleRequirements .............152

Figure 61. Sequential Memory-to-I/O Transfer, Standard Timing

(SearchingisOptional) ...........................154

Figure 62. Sequential I/O-to-Memory Transfer, Standard Timing

(SearchingisOptional) ...........................155

Figure 63. Simultaneous Memory-to-I/O Transfer (Burst and Continuous

Mode) ........................................156

Figure64. SimultaneousMemory-to-I/OTransfer(ByteMode)....157

Figure65. BusRequestandAcceptanceTiming ................159

Figure66. BusReleaseinByteMode ........................160

Figure 67. Bus Release on End-of-Block (Burst and

Continuous Modes) ..............................160

Figure 68. Bus Release on Match (Burst and Continuous Modes) . .161

Figure69. BusReleaseonNotReady(BurstMode) .............162

Figure70. RDYLineinByteMode ..........................163

Figure71. RDYLineinBurstMode .........................164

Figure 72. RDY Line in Continuous Mode ....................165

Figure73. Variable-CycleandEdgeTiming ...................166

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 329 330

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Zilog Z08470 Manual do Utilizador Página 11