Zilog Z08470 Manual do Utilizador descarregar pdf (Página 215)

UM008101-0601 Parallel Input/Output

after this edge has risen. The input portion of Mode 2 operates identically to

Mode 1. Notice that both Port A and Port B must have their interrupts

enabled to achieve an interrupt-driven, bidirectional transfer.

The peripheral must not gate data onto a port data bus while ASTB

active. Bus contention is avoided when the peripheral uses BSTB

to gate

input data onto the bus. The PIO uses the BSTB low level to latch this data.

The data can be disabled from the bus immediately after the strobe rising

edge. This is because the PIO has been designed with a zero hold time

requirement for the data when latching in this mode. This gating structure

can be used by the peripheral.

Figure 9. Port A, Mode 2 (Bidirectional) Timing

Control Mode (Mode 3)

The control mode does not utilize the handshake signals, therefore a normal

port write or port read can be executed at any time. When writing, the data

is latched to output registers with the same timing as Mode 0. ARDY is

forced low whenever Port A is operated in Mode 3. BRDY is held Low

whenever Port B is operated in Mode 3 unless Port A is in Mode 2. In the

latter case, the state of BRDY is not affected.

WR*

Sample

=RD• CE • C/D • IORQ

Data Out

Data In

ARDY

ASTB

Port A

Data Bus

INT

BSTB

BRDY

1 2 ... 210 211 212 213 214 215 216 217 218 219 220 ... 329 330

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