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Z80 CPU Peripherals

User Manual

UM008101-0601 Serial Input/Output

281

IORQ and the corresponding S/A and C/D inputs to the Z80 SIO to

transfer data. The READY output becomes inactive when IORQ and CS

become active. The Ready function can occur internally in the Z80 SIO,

whether it is addressed or not. Therefore, the READY

output becomes

inactive when any CPU data or command transfer occurs. Because the

DMA controller is not enabled when the CPU transfer occurs, the system

continues to function normally.

The Wait function is active only when the CPU attempts to read Z80 SIO

data that has not yet been received, which occurs frequently when block

transfer instructions are used. The Wait function can also become active

(under program control) if the CPU tries to write data while the transmit

buffer is still full. The WAIT

output for either channel becomes active

when the opposite channel is addressed. This active state occurs because

the Z80 SIO is addressed and does not affect software loops or block move

instructions.

Write Register 2

WR2 (Figure 116) is the interrupt vector register and occurs in Channel B

only. V7-V4 and V0 are always returned exactly as written; V3-V1 are

returned as written if the Status Affects Vector (WR1, D2) control bit is 0. If

this bit is 1, they are modified as explained in “Write Register 1” on

page 277.

Table19.WriteRegister2InterruptVector

D7 D6 D5 D4 D3 D2 D1 D0

V7 V6 V5 V4 V3 V2 V1 V0

1 2 ... 296 297 298 299 300 301 302 303 304 305 306 ... 329 330

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