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UM008101-0601 Direct Memory Access

The event sequences for SIO-DMA transfers are described in Table 17 and

Table 18.

Table 17. Receive Event Sequence

Event

Inter-event delay

(clock periods)

SIO receives last bit of character 10-13 latency

SIO RDY

becomes active 2 latency

DMA asserts BUSREQ

1-5 latency

Current CPU machine cycle ends 1 latency, bus occupancy

CPU asserts BUSACK

4 latency, bus occupancy

DMA I/O read cycle begins 4 latency, bus occupancy

DMA memory write cycle begins 2 bus occupancy

DMA terminates BUSREQ

1 bus occupancy

DMA memory write cycle ends 1 bus occupancy

CPU terminates BUSACK

and

regains control of bus

1 bus occupancy

Note: Latency (delay from reception of final data bit to reading of received data) is 22 to

29 clock periods. The system bus is occupied by the DMA for 13 clock periods per byte

transferred.

Table 18. Transmit Event Sequence

Event

Inter-event delay

(clock periods)

SIO transmits last bit of character 5-6 latency

SIO RDY

becomes true 2 latency

DMA asserts BUSREQ

1-5 latency

Current CPU machine cycle ends 1 latency, bus occupancy

CPU asserts BUSACK

4 latency, bus occupancy

DMA memory read cycle begins 3 latency, bus occupancy

1 2 ... 153 154 155 156 157 158 159 160 161 162 163 ... 329 330

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