Zilog Z08470 Manual do Utilizador descarregar pdf (Página 106)

UM008101-0601 Direct Memory Access

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Resets the Interrupt Under Service (IUS) latch in the DMA, thereby

allowing its IEO pin to go High so that lower priority devices can

interrupt.

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Enables the DMA to request the bus again. This occurs only in the

Interrupt on Ready option and only when the Enable DMA control

byte is also used.

For non-Z80 environments, control bytes are provided to simulate these

actions.

Interrupt Daisy-Chains

Multiple DMAs can be chained together by their IEI and IEO lines, as

depicted in Figure 37. In the Z80 Family, the DMA’s location in the IEI/

IEO chain sets priority.

When peripherals simultaneously interrupt the Z80 CPU, the highest

priority peripheral (nearest the +5V end of the daisy-chain) is serviced. The

CPU receives the winning peripheral’s interrupt vector. The IEI/IEO chain

allows only the highest priority interrupting peripheral to place its interrupt

vector on the data bus. In non-Z80 environments that have no interrupt

vectors, the winning peripheral is determined by successively reading the

status of all peripherals.

For a device to have priority, its IEI line must be High. When a device

needs service, it prevents downstream devices from interrupting by pulling

its IEO line Low. The next device in the chain then passes this Low

condition on to other downstream devices by pulling its IEO line Low, and

so on.

Whenever an interrupt is acknowledged (Figure 32), the CPU’s interrupt

structure is disabled. It must subsequently be reenabled by an enable inter-

rupts instruction before other devices can interrupt again. This normally

takes place within the interrupt service routine. When done early in the

service routine, this permits higher priority peripherals to interrupt the CPU

while the latter is still executing that service routine. Thus, nested interrupts

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Zilog Z08470 Manual do Utilizador Página 106