Zilog Z08470 Manual do Utilizador descarregar pdf (Página 21)

100

101

UM008101-0601 Counter/Timer Channels

priority. The CPU bus interface logic allows the CTC device to interface

directly to the CPU with no other external logic. However, port address

decoders and/or line buffers may be required for large systems. A block

diagram of the Z80 CTC is depicted in Figure 1.

Figure 1. CTC Block Diagram

Structure of Channel Logic

The structure of one of the four sets of Counter/Timer channel logic is

illustrated in Figure 2. This logic is composed of:

•

Two registers

•

Two counters

•

Control logic

The registers consist of an 8-bit Time Constant register and an 8-bit

Channel Control register. The counters consist of an 8-bit CPU-readable

down-counter and an 8-bit prescaler.

From

Z80 CPU

Data

Control

CPU

BUS

I/O

Internal

Control

Logic

Interrupt

Logic

Counter/

Timer

Logic

RESET

ZC/TO

IEO

INT

IEI

Internal Bus

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 329 330

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