Zilog Z80180 Manual do Utilizador descarregar pdf (Página 78)

100

101

Z8018x

Family MPU User Manual

UM005003-0703

MMU and RESET

During RESET, all bits of the CA field of CBAR are set to

1 while all bits

of the BA field of CBAR, CBR and BBR are reset to

0. The logical 64KB

address space corresponds directly with the first 64KB

0000H to FFFFH)

of the 1024KB

00000H. to FFFFFH) physical address space. Thus, after

RESET, the Z8X180 begins execution at logical and physical address 0.

MMU Register Access Timing

When data is written into CBAR, CBR or BBR, the value is effective

from the cycle immediately following the I/O write cycle which updates

these registers.

During MMU programming insure that CPU program execution is not

disrupted. The next cycle following MMU register programming is

normally an Op Code fetch from the newly translated address. One

technique is to localize all MMU programming routines in a Common

Area that is always enabled.

1 2 ... 73 74 75 76 77 78 79 80 81 82 83 ... 325 326

Comentários a estes Manuais

Sem comentários

Zilog Z80180 Manual do Utilizador Página 78

Comentários a estes Manuais

Manuais e produtos relacionados com Sensores Zilog Z80180