Zilog Z80180 Manual do Utilizador descarregar pdf (Página 141)

Z8018x

Family MPU User Manual

126

UM005003-0703

6RER/W Receiver Enable — When RE is set to 1, the ASCI

receiver is enabled. When RE is reset to 0, the receiver is

disabled and any receive operation in progress is

interrupted. However, the RDRF and error flags are not

reset and the previous contents of RDRF and error flags

are held. RE is cleared to 0 in IOSTOP mode, and during

RESET.

5TER/W Transmitter Enable — When TE is set to 1, the ASCI

transmitter is enabled. When TE is reset to 0, the

transmitter is disabled and any transmit operation in

progress is interrupted. However, the TDRE flag is not

reset and the previous contents of TDRE are held. TE is

cleared to 0 in IOSTOP mode, and during RESET.

RTS0

R/W Request to Send Channel 0 — When RTS0 is reset to 0,

the

RTS0 output pin goes Low. When RTS0 is set to 1,

the

RTS0 output immediately goes High.

3MPBR/

EFR

R/W Multiprocessor Bit Receive/Error Flag Reset — When

multiprocessor mode is enabled (MP in CNTLB is 1),

MPBR, when read, contains the value of the MPB bit for

the last receive operation. When written to 0, the EFR

function is selected to reset all error flags (OVRN, FE and

PE) to 0. MPBR/EFR is undefined during RESET.

Bit

Position Bit/Field R/W Value Description

1 2 ... 136 137 138 139 140 141 142 143 144 145 146 ... 325 326

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