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Z8018x

Family MPU User Manual

UM005003-0703

141

ASCI to/from DMAC Operation

Operation of the ASCI with the on-chip DMAC channel 0 requires that the

DMAC be correctly configured to use the ASCI flags as DMA request signals.

ASCI and RESET

During RESET, the ASCI status and control registers are initialized as

defined in the individual register descriptions.

Receive and Transmit operations are stopped during RESET. However,

the contents of the transmit and receive data registers (TDR and RDR) are

not changed by RESET.

ASCI Clock

When in external clock input mode, the external clock is directly input to

the sampling rate (¸16/¸64) as depicted in Figure 56.

Figure 56. ASCI Clock

External Clock

Phi

Internal Clock

Phi

Baud Rate Selection

Prescaler Sampling Rate

1 to

1 2 ... 151 152 153 154 155 156 157 158 159 160 161 ... 325 326

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