Zilog Z80180 Manual do Utilizador descarregar pdf (Página 152)

100

101

Z8018x

Family MPU User Manual

UM005003-0703

137

Each ASCI channel control register B configures multiprocessor mode,

parity and baud rate selection.

2 Break

Feature

Enable

R/W 0

Break Feature Enable On

Break Feature Enable Off

1 Break

Detect

(RO)

R/W 0

Break Detect On

Break Detect Off

0 Send

Break

R/W 0

Normal Xmit

Drive TXA Low

ASCI0 Time Constant Low Register (I/O Address: 1AH) (Z8S180/L180-Class Processors

Only)

Bit 76543210

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 00 00 00 0

Note: R = Read W = Write X = Indeterminate ? = Not Applicable

ASCI0 Time Constant High Register (I/O Address: 1BH) (Z8S180/L180-Class Processors

Only)

Bit 76543210

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 00 00 00 0

Note: R = Read W = Write X = Indeterminate ? = Not Applicable

Bit

Position Bit/Field R/W Value Description

1 2 ... 147 148 149 150 151 152 153 154 155 156 157 ... 325 326

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Zilog Z80180 Manual do Utilizador Página 152

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