Zilog Z80180 Manual do Utilizador descarregar pdf (Página 139)

Z8018x

Family MPU User Manual

124

UM005003-0703

4FER Framing Error — If a receive data byte frame is

delimited by an invalid stop bit (that is, 0, should be 1),

FE is set to 1. FE is cleared to 0 when the EFR bit (Error

Flag Reset) of CNTLA is written to 0, when DCD0 is

High, in IOSTOP mode, and during RESET.

3RIER/W Receive Interrupt Enable — RIE must be set to 1 to

enable ASCI receive interrupt requests. When RIE is 1, if

any of the flags RDRF, OVRN, PE, or FE become set to

1, an interrupt request is generated. For channel 0, an

interrupt is also generated by the transition of the external

DCD0

input from Low to High.

2CTS1ER/W Channel 1 CTS

Enable — Channel 1 has an external

CTS1

input which is multiplexed with the receive data

pin (RXS) for the CSI/O (Clocked Serial I/O Port).

Setting CTS1E to 1 selects the CTS1

function and

clearing CTS1E to 0 selects the RXS function.

1TDRER Transmit Data Register Empty — TDRE = 1 indicates

that the TDR is empty and the next transmit data byte is

written to TDR. After the byte is written to TDR, TDRE

is cleared to 0 until the ASCI transfers the byte from TDR

to the TSR and then TDRE is again set to 1. TDRE is set

to 1 in IOSTOP mode and during RESET. When the

external CTS

input is High, TDRE is reset to 0.

0TIER/W Transmit Interrupt Enable — TIE must be set to 1 to

enable ASCI transmit interrupt requests. If TIE is 1, an

interrupt is requested when TDRE is 1. TIE is cleared to 0

during RESET.

Bit

Position Bit/Field R/W Value Description

1 2 ... 134 135 136 137 138 139 140 141 142 143 144 ... 325 326

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Zilog Z80180 Manual do Utilizador Página 139