Zilog Z8F0130 Manual do Utilizador descarregar pdf (Página 99)

eZ8

™

CPU Core

User Manual

UM012820-0810 ADDX Instruction

Attributes

Escaped Mode Addressing

Using Escaped Mode Addressing, address mode ER for the source or des-

tination specifies a working register with 4-bit addressing.

If the high byte of the source or destination address is EEh (11101110b),

a working register is inferred. For example, the operand

EE3h selects

Working Register R3. The full 12-bit address is provided by

{RP[3:0],

RP[7:4], 3h}

To access registers on Page Eh (addresses E00h to EFFh), set the Page

Pointer, RP[3:0], to

Eh and set the Working Group Pointer, RP[7:4], to

the preferred Working Group.

Sample Usage

If Register 634h contains the value 2Eh and Register B12h contains the

value

1bh, the following statement leaves the value 49h in Register

634h, sets the H flag, and clears the C, Z, S, V, and D flags:

ADDX

634h

B12h

Object Code: 08 B1 26 34

Using Escaped Mode Addressing, if Working Register R4 contains the

value

2Eh and Register B12h contains the value 1bh, the following state-

ment leaves the value 49h in Working Register R4, sets the H flag, and

clears the C, Z, S, V, and D flags:

Mnemonic

Destination,

Source

Code

(Hex) Operand 1 Operand 2 Operand 3

ADDX ER1, ER2 08 ER2[11:4] {ER2[3:0],

ER1[11:8]}

ER1[7:0]

ADDX ER1, IM 09 IM {0h,

ER1[11:8]}

ER1[7:0]

1 2 ... 94 95 96 97 98 99 100 101 102 103 104 ... 313 314

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