Zilog Z8F0130 Manual do Utilizador descarregar pdf (Página 30)

100

101

eZ8

™

CPU Core

User Manual

UM012820-0810 Z8

Compatibility

continues to support these instructions. For more information, see the

Addressing Modes on page 27 and the LD on page 164.

The Watchdog Timer Enable During HALT mode instruction, WDH, is

also removed. For information on the Watchdog Timer, refer to the Zilog

Product Specification specific to your Z8 Encore!

device.

Relocation of eZ8 CPU Control Registers

Four control registers within the eZ8 CPU feature new addresses to take

advantage of the larger Register File.

Stack Pointer High and Low Byte Registers

The Stack Pointer Low Byte (SPL) now resides at address FFFh in the

FFEh.

The Register Pointer (RP) now resides at address FFDh in the Register

File.

Flags Register

The Flags Register (FLAGS) now resides at address FFCh in the Register

File.

Compatibility with Z8 CPU

Certain changes to the eZ8 CPU improve over the Z8

CPU but are still

compatible if you choose to migrate to the eZ8 CPU.

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