Zilog Z8F0130 Manual do Utilizador descarregar pdf (Página 23)

eZ8

™

CPU Core

User Manual

UM012820-0810 Architectural Overview

of instruction that was last executed, enabling the subsequent decimal

adjust (DA) operation. Normally, the Decimal Adjust flag cannot be used

as a test condition. After a subtraction, the Decimal Adjust flag is 1. Fol-

lowing an addition, it is 0.

Half Carry Flag

The Half Carry (H) flag is 1 when an addition generates a carry from Bit 3

or a subtraction generates a borrow from Bit 4. The DA instruction con-

verts the binary result of a previous addition or subtraction into the correct

BCD result using the Half Carry flag. As in the case of the Decimal

Adjust flag, the user does not normally access this flag directly.

Condition Codes

The C, Z, S and V flags control the operation of the conditional jump (JP

cc and JR cc) instructions. Sixteen frequently useful functions of the flag

settings are encoded in a 4-bit field called the condition code (cc), which

forms Bits 7:4 of the first Op Code of conditional jump instructions.

Table 2 summarizes the condition codes. Some binary condition codes

can be created using more than one assembly code mnemonic. The result

of the flag test operation determines if the conditional jump executes.

Table 2. Condition Codes

Binary Hex

Assembly

Mnemonic Definition Flag Test Operation

0000 0 F Always False –

0001 1 LT Less Than (S XOR V) = 1

0010 2 LE Less Than or Equal (Z OR (S XOR V)) = 1

0011 3 ULE Unsigned Less Than or Equal (C OR Z) = 1

0100 4 OV Overflow V = 1

0101 5 Ml Minus S = 1

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 313 314

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