Zilog Z16C30 Manual do Utilizador descarregar pdf (Página 61)

4-12

Z16C30 USC

USER'S MANUAL

UM97USC0100

ZILOG

4.7 EDGE DETECTION AND INTERRUPTS (Continued)

While an L/U bit is 1, the state of the associated data bit is

frozen (latched). These two bits remain in this state, re-

gardless of further transitions on the pin, until software

writes a 1 to the L/U bit. This clears the L/U bit to 0 and

“opens” the data latch to once again report and track the

state of the pin, at least for an “instant”. If one or more

enabled transitions occurred while the L/U bit was set, then

L/U is set again right after software writes the 1 to it.

Writing a 0 to an L/U bit has no effect, and the channel

ignores data written to the “data” bits.

One mode in which software can use this logic is to read

the MISR, then immediately write back what it has read.

The software should then look for 1’s in any and all

“interesting” L/U bits, and process/handle all such changes

without rereading the MISR. To obtain the current state of

one of these pins, regardless of the L/U bit, software can

write a 1 to the L/U bit and then immediately read back the

MISR.

RxCUp

14 13 12 11 10 9 8 7 6 5 4 3 2 1 015

RxCDn

TxRDn

TxCDn

CTSUp

DCDDn

RCC

Under

TxCUp

RxRDn

RxRUp

TxRUp

DCDUp

CTSDn

DPLL

DSync

BRG1

BRG0

Figure 4-7. The Status Interrupt Control Register (SICR)

/RxC

14 13 12 11 10 9 8 7 6 5 4 3 2 1 015

RxCL/U TxRL/UTxCL/U

/CTS

DCDL/U

RCC

Under

L/U

/TxC

RxRL/U /RxREQ /TxREQ

/DCD

CTSL/U

DPLL

DSync

L/U

BRG1

L/U

BRG0

L/U

Figure 4-8. The Miscellaneous Interrupt Status Register (MISR)

UM009402-0201

1 2 ... 56 57 58 59 60 61 62 63 64 65 66 ... 207 208

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