
8-35
Z16C30 USC
®
USER'S MANUAL
ZILOG
UM97USC0100
"TxFIFO Status" if last TCSR15-12 command 4-7 was 5
"Tx/Int level" if last TCSR15-12 command 4-7 was 6
"TxREQ level" if last TCSR15-12 command 4-7 was 7
Transmit Interrupt Control Register (TICR) Register Address 0 b 11011
Pre
Sent IA
Bit(s)
Field/Bit
Name
Conditions
/Context
Description
RW
Status
Ref Chapter: Section
14 13 12 11 10 9 8 7 6 5 4 3 2 1 015
Idle
Sent
IA
Abort
Sent
IA
EOF/
EOM
Sent IA
CRC
Sent
IA
Wait2
Send
Tx
Under
IA
TC1R
Sel
TICR15-8 the number of empty character/byte/octet
entries in the TxFIFO, above which to request
Transmit DMA transfer
RW 6: DMA Requests by the
Receiver and Transmitter
7 written to
TCmd
(TCSR15-
12) since 5
or 6 written
there
TICR15-8 the number of empty character/byte/octet entries
in the TxFIFO, above which to request a Transmit
Data Interrupt
RW 7: Transmit Data interrupts
6 written to
TCmd
(TCSR15-
12) since 5
or 7 written
there
TICR15-8 the number of empty character/byte/octet entries
currently in the TxFIFO
RO 5:The Data Registers
and the FIFOs
5 written to
TCmd
(TCSR15-
12), or
Reset,
since 6 or 7
written
there
TICR7 1=arm interrupts on Preamble Sent (TCSR7) RW 7: Transmit Status Interrupt
Sources and IA Bits
PreSent IA
TICR6 1=arm interrupts on IdleSent (TCSR6)IdleSent IA
TICR5 1=arm interrupts on AbortSent (TCSR5)AbortSent
IA
TICR4 1=arm interrupts on EOF/EOM Sent (TCSR4)EOF/EOM
Sent IA
TICR3 1=arm interrupts on CRCSent (TCSR3)CRCSent IA
5: Synchronizing Frames/
Messages with Software
Response
TICR2 1=hold Transmitter from sending each
frame/message until software issues "Send
Message/Frame" command
RW
Wait2Send
7: Transmit Status Interrupt
Sources and IA Bits
TICR1 1=arm interrupts on TxOver (TCSR1) RWTxUnder IA
TICR0 0=select Time Constant value for reading TC1R;
1=capture current count for reading TC1R
RWTC1R Sel 4: Tx and Rx Clocking: The
Baud Rate Generators
Sync
H/SDLC
Sync
Sync
Sync
RW = Read/Write, RO = Read Only, WO = Write Only – for other codes see p. 8-10.
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