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4-3
Z380
™
USER'S MANUAL
ZILOG
DC-8297-03
4.2.4 Direct Address (DA)
When Direct Address mode is used, the data processed is
at the location whose memory or I/O port address is in the
instruction.
Instruction Memory or
OPERATION I/O Port
ADDRESS → OPERAND
The operand value is the contents of the location whose
address is in the instruction.
Depending on the instruction, the operand specified by
DA mode is either in the I/O address space (I/O instruction)
or memory address space (all other instructions).
This mode is also used by Jump and Call instructions to
specify the address of the next instruction to be executed.
(The address serves as an immediate value that is loaded
into the program counter.)
Also, DDIR Immediate Data Directives are used to expand
the direct address to 24 or 32 bits. Operand width is
affected by LW bit status for the load and exchange
instructions.
Example of DA mode:
1. Load BC register from memory location 00005E22H in Word mode
LD BC, (5E22H) ;Load BC with the data in address
;00005E22H
BC
Before instruction execution 1234
After instruction execution 0301
Memory location 00005E22 01
00005E23 03
2. Load BC register from memory location 12345E22H in Word mode
DDIR IW ;extend direct address by one word
LD BC, (12345E22H) ;Load BC with the data in address
;12345E22H
BC
Before instruction execution 1234
After instruction execution 0301
Memory location 12345E22 01
12345E23 03
3. Load BC register from memory location 12345E22H in Long Word mode
DDIR IW,LW ;extend direct address by one word,
;and operation in Long Word
LD BC, (12345E22H) ;Load BC with the data in address
;12345E22H
BCz BC
Before instruction execution 1234 5678
After instruction execution 0705 0301
Memory location 12345E22 01
12345E23 03
12345E24 05
12345E25 07
- Z80380 CPU 1
- 'S MANUAL 1
- CHAPTER 1 3
- 1.1 INTRODUCTION (Continued) 4
- 1.2 CPU ARCHITECTURE 5
- 1.2.1 Modes of Operation 5
- 1.2.2 Address Spaces 5
- 1.2.3 Data Types 6
- 1.2.4. Addressing Modes 6
- 1.2.5. Instruction Set 6
- 1.2.6 Exception Conditions 6
- 1.3.1 High Throughput 7
- (Continued) 8
- 1.4 SUMMARY 8
- SER'S MANUAL 10
- 2.4 MEMORY ADDRESS SPACE 12
- USER'S MANUAL 15
- DC-8297-03 15
- CHAPTER 2 16
- CHAPTER 3 23
- 3.2 DECODER DIRECTIVES 24
- CHAPTER 4 26
- 4.2.3 Indirect Register (IR) 27
- 4.2.4 Direct Address (DA) 28
- 4.2.5 Indexed (X) 29
- 4.3 DATA TYPES 34
- CHAPTER 5 35
- 5.2.7 Condition Codes 37
- SWAP, and PUSH/POP Group 41
- 5.5.8 Program Control Group 46
- 5.5.11 CPU Control Group 50
- 5.5.12 Decoder Directives 51
- 5.7 EXECUTION TIME 52
- ADD WITH CARRY (BYTE) 54
- ADD WITH CARRY (WORD) 55
- ADD (BYTE) 57
- ADD (WORD) 58
- ADD TO STACK POINTER (WORD) 59
- AND (BYTE) 61
- AND (WORD) 62
- BIT TEST 63
- BANK TEST 64
- CALL RELATIVE 66
- COMPLEMENT CARRY FLAG 67
- COMPARE (BYTE) 68
- COMPARE (WORD) 69
- COMPARE AND DECREMENT (BYTE) 70
- COMPARE AND INCREMENT (BYTE) 72
- COMPLEMENT ACCUMULATOR 74
- COMPLEMENT HL REGISTER (WORD) 75
- DECIMAL ADJUST ACCUMULATOR 76
- DECODER DIRECTIVE 77
- DECREMENT (BYTE) 78
- DECREMENT (WORD) 79
- DISABLE INTERRUPTS 80
- DIVIDE UNSIGNED (WORD) 81
- ENABLE INTERRUPTS 83
- EXCHANGE REGISTER (WORD) 86
- EXCHANGE WITH ACCUMULATOR 89
- EXTEND SIGN (BYTE) 91
- EXTEND SIGN (WORD) 92
- INTERRUPT MODE SELECT 97
- INPUT (BYTE) 98
- INPUT (WORD) 99
- INPUT ACCUMULATOR 100
- INPUT (FROM PAGE 0) 101
- INCREMENT (BYTE) 104
- INCREMENT (WORD) 105
- INPUT AND DECREMENT (BYTE) 106
- INPUT AND DECREMENT (WORD) 107
- INPUT AND INCREMENT (BYTE) 110
- INPUT AND INCREMENT (WORD) 111
- JUMP RELATIVE 115
- LOAD ACCUMULATOR 116
- LOAD IMMEDIATE (BYTE) 117
- LOAD IMMEDIATE (WORD) 118
- LOAD REGISTER (BYTE) 120
- LOAD REGISTER (WORD) 121
- LOAD STACK POINTER 123
- LOAD I REGISTER (WORD) 126
- LOAD CONTROL REGISTER (BYTE) 127
- LOAD AND DECREMENT (BYTE) 130
- LOAD AND DECREMENT (WORD) 131
- LOAD AND INCREMENT (BYTE) 134
- LOAD AND INCREMENT (WORD) 135
- MULTIPLY UNSIGNED (BYTE) 138
- MODE TEST 139
- MULTIPLY (WORD) 140
- MULTIPLY UNSIGNED (WORD) 141
- NEGATE ACCUMULATOR 142
- NEGATE HL REGISTER (WORD) 143
- NO OPERATION 144
- OR (BYTE) 145
- OR (WORD) 146
- OUTPUT DECREMENT MEMORY 147
- OUTPUT INCREMENT MEMORY 151
- OUTPUT (BYTE) 155
- OUTPUT (WORD) 156
- OUTPUT ACCUMULATOR 157
- OUTPUT (TO PAGE 0) 158
- OUTPUT AND DECREMENT (BYTE) 161
- OUTPUT AND DECREMENT (WORD) 162
- OUTPUT AND INCREMENT (BYTE) 163
- OUTPUT AND INCREMENT (WORD) 164
- POP ACCUMULATOR 165
- POP CONTROL REGISTER 166
- POP REGISTER 167
- PUSH ACCUMULATOR 168
- PUSH CONTROL REGISTER 169
- PUSH IMMEDIATE 170
- PUSH REGISTER 171
- RESET BIT 172
- RESET CONTROL BIT 173
- RETURN FROM BREAKPOINT 175
- RETURN FROM INTERRUPT 176
- ROTATE LEFT (BYTE) 178
- ROTATE LEFT (WORD) 179
- ROTATE LEFT (ACCUMULATOR) 180
- ROTATE LEFT CIRCULAR (BYTE) 181
- ROTATE LEFT CIRCULAR (WORD) 182
- ROTATE LEFT DIGIT 184
- ROTATE RIGHT (BYTE) 185
- ROTATE RIGHT (WORD) 186
- ROTATE RIGHT (ACCUMULATOR) 187
- ROTATE RIGHT CIRCULAR (BYTE) 188
- ROTATE RIGHT CIRCULAR (WORD) 189
- ROTATE RIGHT DIGIT 191
- SUBTRACT WITH CARRY (BYTE) 193
- SUBTRACT WITH CARRY (WORD) 194
- SET CARRY FLAG 196
- SET CONTROL BIT 198
- SHIFT LEFT ARITHMETIC (BYTE) 199
- SHIFT LEFT ARITHMETIC (WORD) 200
- SHIFT RIGHT ARITHMETIC (BYTE) 202
- SHIFT RIGHT ARITHMETIC (WORD) 203
- SHIFT RIGHT LOGICAL (BYTE) 204
- SHIFT RIGHT LOGICAL (WORD) 205
- SUBTRACT (BYTE) 206
- SUBTRACT (WORD) 207
- TEST (BYTE) 211
- TEST I/O PORT 212
- EXCLUSIVE OR (BYTE) 213
- EXCLUSIVE OR (WORD) 214
- CHAPTER 6 215
- 6.2 INTERRUPTS (Continued) 216
- 6.2.2 Interrupt Control 216
- 6.3 TRAP INTERRUPT 218
- 6.7 RETI INSTRUCTION 220
- CHAPTER 7 222
- APPENDIX A 225
- APPENDIX B 228
- APPENDIX C 243
- APPENDIX D 258
- APPENDIX E 262
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