Zilog EZ80F91 Manual do Utilizador

Copyright ©2008 by Zilog®, Inc. All rights reserved.www.zilog.comeZ80Acclaim!® Microcontrollers eZ80F91 Development KitUser ManualUM014220-0508

eZ80F91 Development KitUser ManualUM014220-0508 Introduction5Figure 2. The eZ80Acclaim!® Development KitDEABCNote: The above is an example only and mi

eZ80F91 Development KitUser ManualUM014220-0508 Introduction6Figure 3 displays the eZ80F91 Module segmented into its key blocks, as shown in the legen

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit7eZ80 Development KitThis section describes the eZ80Acclaim!® Development Kit hard

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit8Figure 4. Basic eZ80Acclaim!® Development Kit Block DiagrameZ80ModuleInterfaceRS2

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit9Physical DimensionsThe dimensions of the eZ80Acclaim!® Development Kit PCB is 177

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit10Operational DescriptionThe eZ80Acclaim!® Development Kit can accept any eZ80®-co

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit11The description of these five signals are provided below.Enable Flash—When activ

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit12Figure 6. eZ80Acclaim!® Development Kit Peripheral Bus Connector Pin Configurati

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit13Table 3. eZ80Acclaim!® Development Kit Peripheral Bus Connector Identification—J

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit1423 A5 Bidirectional Yes24 A17 Bidirectional Yes25 DIS_ETHOutput Low No26 EN_Flas

eZ80F91 Development KitUser ManualUM014220-0508 Revision HistoryiiRevision HistoryEach instance in Revision History reflects a change to this document

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit15I/O ConnectorFigure 7 displays the pin layout of the I/O Connector in the 50-pin

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit16Figure 7. eZ80Acclaim!® Development Kit I/O Connector Pin Configuration—JP2PB1PB

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit17Table 4. eZ80Acclaim!® Development Kit I/O Connector Identification—JP21 Pin # S

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit1824 PD2 Bidirectional Yes25 PD1 Bidirectional Yes26 PD0 Bidirectional Yes27 TDO I

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit19Internal On-Chip Flash MemoryTo program internal on-chip Flash memory, the JP3 s

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit20Thermostat Application Module (not provided in the kit) is an example of an appl

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit21PC[7:0] 39,41,43,45,47,49,51,53Port C, Bit [7:0] IN/OUTID_[2:0] 6,8,10 eZ80Accla

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit22I/O FunctionalityThe eZ80Acclaim!® Development Kit provides I/O functionality. T

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit23GPIO EmulationGPIO is emulated with the use of the GPIO Output Control Register

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit24Modem ResetThe Modem Reset signal, MRESET, is used to reset an optional socket m

eZ80F91 Development KitUser ManualUM014220-0508 SafeguardsiiiSafeguardsThe following precautions must be observed when working with the devices descri

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit25Bits 6 and 7 in Table 15 are the control bits for the user triggers. If either b

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit26Figure 9. Embedded Modem Socket Interface—J1, J5, and J9Table 11. Connector J5Pi

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit27Components P4, T1, C3, C4, and U11 provide the phone line interface to the modem

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit28The tested modem for this eZ80F91 Development Kit is a MultiTech Sys-tems (forme

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit29address decoder, implemented in the Generic Array Logic device, GAL22LV10D (U10)

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit30Figure 10. Memory Map of the eZ80Acclaim!® Development Kit and eZ80F91 ModuleC00

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit31Chip Selects and Wait States—As seen in the memory map in Figure 10, Flash memor

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit32Bits 0–6 in Table 9 are LED anode bits. They must be set High (1) and their corr

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit33Data Carrier DetectThe Data Carrier Detect (DCD) signal at D1 indicates that a g

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit34RESETThe Reset push button switch, SW4, resets the eZ80® CPU and the eZ80Acclaim

eZ80F91 Development KitUser ManualUM014220-0508 Table of ContentsivTable of ContentsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . .

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit35Jumper J7The J7 jumper connection controls Flash boot loader programming. When t

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit36The silk-screened label on the eZ80Acclaim!® Development Kit for jumper J11 is i

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit37Jumper J14The J14 jumper connection controls the polarity of the Ring Indicator.

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit38disabled if the RS-485 circuit is enabled. When the shunt is placed, the RS-485

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit39Jumper J19The J19 jumper connection selects the range of memory addresses for th

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit40Jumper J20The J20 jumper connection controls the selection of the external chip

eZ80F91 Development KitUser ManualUM014220-0508 eZ80 Development Kit41ConsoleConnector P2 is the RS-232 terminal, which can be used for observing the

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module42eZ80F91 ModuleThis section describes the eZ80F91 Module hardware, its interfaces and k

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module43eZ80F91 device (a generic feature of the eZ80® family when it is used in native mode).

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module44Essentially, after the eZ80F91 device accesses Flash memory, a time duration of 8.8 n

eZ80F91 Development KitUser ManualUM014220-0508 Table of ContentsvIrDA Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module45Figure 12. Physical Dimensions of the eZ80F91 ModuleJP11JP21Y3P2CR1U6C1C11C12C18C19C20

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module46Figure 13 displays the top layer silkscreen of the eZ80F91 Module.Figure 13. eZ80F91 M

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module47Figure 14 displays the bottom layer silkscreen of the eZ80F91 Module.Operational Descr

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module48eZ80F91 Module MemoryStatic RAMThe eZ80F91 Module features 512 KB of fast SRAM. Acces

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module49condition. The RESET pin on the I/O connector reflects the status of the RESET line. I

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module50Figure 15 displays the eZ80F91 Module IrDA hardware connections.The eZ80F91 Module fea

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module51//Init_IRDA// Make sure to first set PD2 as a port bit, an output and set it Low.PD_AL

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module52eZ80Acclaim! Development Kit’s JP2 socket. When the module is mounted correctly, it wi

eZ80F91 Development KitUser ManualUM014220-0508 eZ80F91 Module53Figure 17. Inserting a New Plug ConfigurationFigure 17 is for the 9 VDC power supply.

eZ80F91 Development KitUser ManualUM014220-0508 ZPAK II54ZPAK IIZPAK II is a debug tool used to develop and debug hardware and soft-ware. It is a netw

eZ80F91 Development KitUser ManualUM014220-0508 Introduction1IntroductionZilog’s eZ80F91 Development Kit provides a general-purpose platform for evalu

eZ80F91 Development KitUser ManualUM014220-0508 ZDS II55ZDS IIZilog Developer Studio II (ZDS II) Integrated Development Environment is a complete stan

eZ80F91 Development KitUser ManualUM014220-0508 Troubleshooting56TroubleshootingOverviewBefore contacting Zilog Customer Support to submit a problem r

UM014220-0508 SchematicseZ80F91 Development KitUser Manual57SchematicseZ80F91 Development PlatformFigure 18 through Figure 22 displays the layout of

UM014220-0508 SchematicseZ80F91 Development KitUser Manual58Figure 19. eZ80F91 Development Platform Schematic Diagram, #2 of 55544332211D DC CB BA AL

UM014220-0508 SchematicseZ80F91 Development KitUser Manual59Figure 20. eZ80F91 Development Platform Schematic Diagram, #3 of 55544332211D DC CB BA AM

UM014220-0508 SchematicseZ80F91 Development KitUser Manual60Figure 21. eZ80F91 Development Platform Schematic Diagram, #4 of 55544332211D DC CB BA AR

UM014220-0508 SchematicseZ80F91 Development KitUser Manual61Figure 22. eZ80F91 Development Platform Schematic Diagram, #5 of 5—RS-485 CableLENGTH = 5

UM014220-0508 Schematic DiagramseZ80F91 Development KitUser Manual62eZ80F91 ModuleFigure 23 through Figure 25 displays the layout of the eZ80F91 Modu

UM014220-0508 Schematic DiagramseZ80F91 Development KitUser Manual63Figure 24. eZ80F91 Module Schematic Diagram, #2 of 3—CPU and PHY5544332211D DC CB

UM014220-0508 Schematic DiagramseZ80F91 Development KitUser Manual64Figure 25. eZ80F91 Module Schematic Diagram, #3 of 3—Module Memory5544332211D DC

eZ80F91 Development KitUser ManualUM014220-0508 Introduction2– 9 VDC power connector– Telephone jack•eZ80F91 Module:– eZ80F91 device operating at 50

eZ80F91 Development KitUser ManualUM014220-0508 Appendix A—General Array Logic Equations65Appendix A—General Array Logic EquationsThis appendix shows

eZ80F91 Development KitUser ManualUM014220-0508 Appendix A—General Array Logic Equations66nCS2,nEX_FL_DIS, //disables Flash on the expansion //module,

eZ80F91 Development KitUser ManualUM014220-0508 Appendix A—General Array Logic Equations67//A18=A2,A17=A1,A16=A0outputnCS_EX/* synthesis loc="P17

eZ80F91 Development KitUser ManualUM014220-0508 Appendix A—General Array Logic Equations68//expansion module //Flash enabled if this is 0//wire nDIS_F

eZ80F91 Development KitUser ManualUM014220-0508 Appendix A—General Array Logic Equations69// // module F92_em_pal(nDIS_EM,nEM_EN,A0,A1,A2,A3,A4,A5,A6,

eZ80F91 Development KitUser ManualUM014220-0508 Appendix A—General Array Logic Equations70A2 /* synthesis loc="P10"*/,A3 /* synthesis loc=&q

eZ80F91 Development KitUser ManualUM014220-0508 Appendix A—General Array Logic Equations71assign nAN_WR = ~((nDIS_EM==1)&(nWR==0)&(nEM_EN==0)&

eZ80F91 Development KitUser ManualUM014220-0508 Customer Support72Customer SupportFor answers to technical questions about the product, documentation,

eZ80F91 Development KitUser ManualUM014220-050873DO NOT USE IN LIFE SUPPORTLIFE SUPPORT POLICYZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRIT

eZ80F91 Development KitUser ManualUM014220-0508 Introduction305/30/06—The following components are not populated on the board:– U11: Triac, SCR Phone

eZ80F91 Development KitUser ManualUM014220-0508 Introduction4Figure 2 on page 5 displays eZ80Acclaim!® Development Kit segmented into its key blocks,