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CPU

User Manual

UM001604-0108 Interrupts

101

Interrupt Mask Register Initialization

The Interrupt Mask Register individually or globally enables or disables the six interrupt

requests (see Figure 97 on page 102). When bit 0 to bit 5 are set to 1, the corresponding

interrupt requests are enabled. Bit 7 is the master enable and must be set before any of the

individual interrupt requests can be recognized. Resetting bit 7 globally disables all of the

interrupt requests. Bit 7 is set and reset by the EI and DI instructions. It is automatically

reset during an interrupt service routine and set following the execution of an Interrupt

Return (IRET) instruction.

Bit 7 must be reset by the DI instruction before the contents of the Interrupt Mask Register

or the Interrupt Priority Register are changed except:

•

Immediately after a hardware reset

•

Immediately after executing an interrupt service routine and before IMR bit 7 has

been set by any instruction

B Bit 2 0 IRQ2 IRQ0

1IRQ0IRQ2

A Bit 5 0 IRQ5 IRQ3

1IRQ3IRQ5

Table 20. Interrupt Group Priority

Bit Pattern Group Priority

Bit 4 Bit 3 Bit 0 High Medium Low

0 0 0 Not Used

00 1 C A B

01 0 A B C

01 1 A C B

10 0 B C A

10 1 C B A

11 0 B A C

1 1 1 Not Used

Table 19. Interrupt Priority (Continued)

Group Bit Value

Priority

Highest Lowest

1 2 ... 103 104 105 106 107 108 109 110 111 112 113 ... 259 260

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