Zilog EZ80L92 Manual do Utilizador descarregar pdf (Página 26)

eZ80L92 Development Kit

User Manual

Operational Description UM012913-0407

ID_[2:0] 6,8,10 eZ80Acclaim!

Development

Platform ID

Output

CON_DIS

12 Console Disable Input If a shunt is installed between

pins 12 and 14, the Console

function on the eZ80Acclaim!

Development Platform is

disabled.

Reserved 16,18

PD[7:0] 22,24,26,

28,30,32,

34,36

Port D, Bit[7:0] Bidirectional

PB[7:0] 40,42,44,

46,48,50,

52,54

Port B, Bit[7:0] Bidirectional

Table 5. CPU Bus Connector J8*

Signal Pin No. Function Direction

A[0:7] 3–10 Address Bus, Low Byte Output

A[8:15] 13–20 Address Bus, High Byte Output

A[16:23] 23–30 Address Bus, Upper Byte Output

33 READ Signal Output

RESET

35 Push Button Reset Output

Note: All the signals except BUSACK and INSTRD are driven by low-voltage CMOS technology

(LVC) drivers.

Table 4. General-Purpose Port Connector J6* (Continued)

Signal Pin No. Function Direction Notes

Note: All signals are driven directly by the CPU.

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 85 86

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